” Research is more about discovering problems than inventing solutions ..”
“Scientific research consists in seeing what everyone else has seen, but thinking what no one else has thought..”
Research Theme
My main research area is in the design and VLSI implementation of embedded signal processing and communications systems. I have primarily focused on the physical (PHY) layer design and implementation aspects of wireless communications systems, with applications to 3GPP (W-CDMA, HSPA, LTE), 3GPP2 (1x EV-DO, UMB), Wi-Fi (802.11n/ac/ax), WiGig (802.11ad) and mobile WiMax (802.16e) standards. The objective of my research is to optimize the design tradeoff between algorithmic performance and implementation complexity of an embedded system, subject to constraints on performance, power, area, reliability, and standards compliance.
The performance of a VLSI system is a function of a complex mix of parameters that span the algorithm, architecture, logic/circuit style, and physical design spaces. With rapidly evolving modern day applications that constantly stretch performance measures to extreme limits, the complexity of this diverse interaction has become intractable. At the heart of this space lies the recurring theme of designing efficient communications systems at affordable implementation complexity. One important example can be drawn from coding theory, which has always sought after designing good error-correcting codes that can be decoded at low implementation cost. Not until the advent of turbo codes whose decoding algorithm is amenable for efficient hardware implementation, has capacity-approaching codes been practically deployed in modern communications systems.
Optimized solutions to this problem require an understanding of the system at various levels of abstraction, starting with modeling and characterization of achievable bounds (e.g., upper bound on BER vs. SNR), an understanding of the algorithms that can potentially achieve these bounds, quantifying tradeoffs in these bounds versus implementation complexity (e.g., tolerable loss in bit-rate and corresponding savings in implementation cost), using these tradeoffs to perform algorithmic optimizations to reduce implementation complexity (e.g., devising architecture-aware algorithms), developing optimized architectures and RTL models that meet certain target specifications in terms of speed, area and power (e.g., tradeoffs between parallel vs. serial architectures), and mapping these architectures onto hardware through automated synthesis or through custom IC design approach (e.g., devising a reconfigurable decoder core). I have based my research theme on a global system-wide approach that emphasizes depth and breadth of knowledge in all four areas of algorithms, architectures, logic/circuits, and physical back-end design. The objective is to enable the smart and efficient design of complex VLSI embedded signal processing systems in a coherent and analytical approach through profound understanding and characterization of their implementation aspects from all four angles.
Current Research
My current research focuses on the following areas:
- Software-defined modems for 5G wireless networks
- Device-to-device communications with application to LTE-Direct
- MIMO detection, multi-user MIMO receiver design
- Low-power multi-Gbps LDPC decoders: Algorithms, architectures, ASIC design
- Carrier aggregation receiver design
- Low-power cryptography engines
- Biomedical signal processing for brain-machine interfaces based on the lambda-hypothesis
Past Research
The performance of a VLSI system in general is function of a complex mix of parameters that span the algorithm, architecture, logic/circuit style, and physical design space. With rapidly evolving modern day applications that constantly stretch performance measures to extreme limits (e.g., continuous increase in uplink and downlink data rates in wireless applications), the complexity of this diverse interaction has become intractable. At the heart of this space lies the recurring theme of designing efficient communications systems (viz. good bit-error rate versus signal-to-noise ratio (SNR)) at affordable implementation complexity (e.g., solutions that can be integrated efficiently on a chip and can operate with limited battery power). One important example can be drawn from coding theory, which has always sought after designing good error-correcting codes that can be decoded at low implementation cost. Not until the advent of turbo codes whose decoding algorithm is amenable for efficient hardware implementation, has capacity-approaching codes been practically employed in modern communications systems.
Optimized solutions to this problem require an understanding of the system at various levels of abstraction, starting with modeling and characterization of achievable bounds (e.g., upper bound on bite-rate vs. SNR), an understanding of the algorithms that can potentially achieve these bounds, quantifying tradeoffs in these bounds versus implementation complexity (e.g., tolerable loss in bit-rate and corresponding savings in implementation cost), using these tradeoffs to perform algorithmic optimizations to reduce implementation complexity (e.g., devising architecture-aware algorithms), developing optimized architectures and RTL models that meet certain target specifications in terms of speed, area and power (e.g., tradeoffs between parallel architectures vs. serial architectures), and mapping these architectures onto hardware through automated synthesis or through custom IC design approach (e.g., devising a programmable decoder core).
I have based my research theme on a global system-wide approach that emphasizes depth and breadth of knowledge in all four areas of algorithms, architectures, logic/circuits, and physical back-end design. The objective is to enable the smart and efficient design of complex VLSI embedded signal processing systems in a coherent and analytical approach through profound understanding and characterization of their implementation aspects from all four fronts.
Details about past projects are found in this document.