• QPSK demodulator with carrier frequency/phase offset errors and symbol timing errors

SpaceX, Los Angeles, CA, USA, Jul. 19, 2016.

  • On parallelizing serially-pruned permutations and their application to iterative channel coding

CAMS Workshop on Coding Theory

American University of Beirut, AUB, Apr. 21–21, 2014, (invited talk).

[Presentation]

  • Design methodologies of energy aware software and hardware architectures for parallel platforms

Middle East Energy Efficiency Research (MER) Annual Review

Abu Dhabi, UAE, Dec. 2010.

  • Introduction to semiconductor manufacturing process

IEEE Silicon Valley Workshop

American University of Beirut, AUB, Apr. 2010, (invited talk).

  • On the VLSI design of high-performance LDPC decoders

International Workshop on VLSI Architectures for LDPC Codes Decoders, Dipartimento di Informatica, University of Pisa, Pisa, Italy, Oct. 2006, (invited talk).

  • VLSI design and implementation of Gbps SPCM decoders

Trellisware Technologies, San Diego, CA, USA, Nov.2005 (invited talk).

  • VLSI design of sparse parity-check matrix decoders

Visitor Seminar Series

EE Department, University of California Los Angeles (UCLA), CA, USA, Nov. 2005.

  • VLSI design for high-speed sparse parity-check matrix decoders

39th Asilomar Conference on Signals, Systems and Computers (ASILOMAR), Pacific Grove, CA, USA, Nov. 1, 2005, (invited talk).

  • Design and implementation of high-performance LDPC decoders

IEEE Communication Theory Workshop (CTW),

Park City, UT, USA, Jun. 2005, (invited talk).

  • Decoder architectures for LDPC and repeat-accumulate codes

Graduate Seminar

University of Texas at Dallas, Rischardson, TX, USA, Dec. 3, 2004.

  • High-performance decoders for regular and irregular repeat-accumulate codes

IEEE Global Communications Conference (GLOBECOM), Dallas, TX, USA, Nov./Dec. 2004.

  • VLSI design of low-density parity-check decoders

VLSI & Wireless Networking and Communications Seminar Series

Dep. of ECE, University of Texas at Austin, Austin, TX, USA, Oct. 15, 2004,(invited talk).

  • A design methodology for high-performance LDPC decoders

ECE Graduate Seminar Series

Dep. of ECE, American University of Beirut, AUB, Lebanon, Apr. 2004.

  • On the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder ar- chitectures

Conference on Information Sciences and Systems (CISS)

Johns  Hopkins  University,  Baltimore,  MD,  USA, Mar. 13 2003.

  • On the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder archi- tectures

CSL Communications Group Seminar Series

University  of  Illinois  at  Urbana-Champaign,  Urbana,  IL,  USA, Feb. 24, 2003.

  • VLSI architectures for iterative channel decoders

R & D group, Texas Instruments, Dallas,  TX, USA, Feb.  6, 2003, (invited talk).

  • Memory-efficient turbo decoder architectures for LDPC codes

IEEE Workshop on Signal Processing Systems (SiPS), San Diego, CA, USA, Oct. 17, 2002.

  • Low-power VLSI decoder architectures for LDPC codes

International Symposium on Low Power Electronics and Design (ISLPED), Monterey, CA, USA, Aug. 14, 2002.

  • Design methodology for high-speed iterative decoder architectures

IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Phoenix, AZ, USA, May 15, 2002.

  • Construction of LDPC codes from Ramanujan graphs

Conference of Information Sciences and Systems (CISS)

Dept. of Electrical Engineering, Princeton University, NJ, USA, Mar. 21, 2002.

  • Low-density codes on Ramanujan graphs: Construction and decoder architectures

CSL Communications Group Seminar Series

Dept. of ECE, University of Illinois at Urbana-Champaign, IL, USA, Mar. 18, 2002.

  • EDGE: Enhanced data for GSM evolution

CSL Communications Group Seminar Series

Dept. of ECE, University of Illinois at Urbana-Champaign, IL, USA, Sep. 10, 2000.

  • Instruction scheduling for low power on dynamically variable voltage processors

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Kaslik, Lebanon, Dec. 19, 2000.

  • FPGA-based Internet Protocol version-6 router

International Conference on Computer  Design  (ICCD)

Austin,  TX, USA, Oct. 6, 1998.