The IPF is a self-aware hardware architecture that predicts potential hardware failures and accommodates for them before they occur. Such a system can be implemented in a pacemaker, for example, where it can significantly reduce the risk of sudden faulty behaviors or shutdowns, hence saving a patient’s life. The project was thus split into four parts, with each part being assigned to one student.

First, the circuit prioritizes the execution of certain functions to avoid any error in the operation of the device, which are the safety critical tasks. In contrast, in best effort situations, the circuit aims to optimize its performance via frequency modification or class migration. This decision making is achieved through the Learning Classifier Table, a self-aware machine learning block modeled by Ali.

The model is based on reinforcement learning that predicts the best action that needs to be taken, such that the proper functioning of the device is ensured. Secondly, based on the design the team is working on, 4 different processing units are needed to be connected in the IPF, using the Network on Chip (NoC). Implemented by Aya, NoC is a network-based communications system that makes sure both the safety critical and best effort tasks are being communicated, with a priority given to safety critical tasks. The network was further tested to make sure it could handle stress while evaluating different design alternatives and picking the optimal one. Moreover, in case a faulty behavior is detected in one of the processors, the presence of a monitoring unit is crucial to make sure the transfer of the tasks to another processor is achievable.